Re: the period of Timer 1 interrupt is twice unexpectedly (ysaitoysaito)

Dear thackerp
Hi
 I found below

bit 6-0 PBDIV<6:0>: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x  7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)

 
 And  I understand  default value is  1/2 by the last two codes.
It seems that this is a little bit difficult to find.   I have checked above register many times for whole  a day.
Thank you very much indeed .
 
best  regards
ysaito